The present invention relates generally to encoders, data detecting semiconductor integrated circuits applicable to such encoders and dynamic sense amplifiers, and more particularly to an encoder for sequentially efficiently encoding, in the order of predetermined priories, a plurality of match address signals from a number of blocks in a content addressable bulk memory and the like, a semiconductor integrated circuit for use in an encoder in the way of detecting the number of data which is increasing or decreasing as number of match addresses to be encoded is detected, and to a semiconductor integrated circuit provided with a dynamic differential current detection circuit for detecting a differential current existing in between a reference current line and a signal line and used for detecting the timing of terminating the operation of encoding a match address signal being encoded, together with a dynamic sense amplifier to be used for the purpose.
Heretofore, associative memories, that is, fully parallel CAMs (Content Addressable Memories), have been widely known as semiconductor storage circuits having the functions of performing the match detection of retrieval data and stored data concurrently in terms of all bits and outputting the match address of stored data or stored data (see "Design Of CMOS VLSI," pp 176-177, edited by Tetsuya Iizuka and supervised by Takuo Sugano, published by Baifukan, Apr. 25, 1989).
Content-addressed retrieval, instead of retrieval by means of physical memory addresses, is common to content addressable memories (CAMs). Therefore, the basic function of CAM, unlike an ordinary memory, is to input retrieval data so as to output a word address at which data matching the retrieval data has been stored.
However, only one word is not necessarily matching and there may be a plurality of them. When the plurality of match words are obtained like this, a correct encode output is unavailable with an ordinary encoder.
Consequently, CAM is equipped with a priority encoder for encoding and outputting a plurality of match (hit) signals in the order of predetermined priorities.
In a bulk CAM, however, the number of words is generally very large in contrast to the word length. For this reason, a cell array is divided into a plurality of blocks and it is an important problem how priority encoders are arranged. In other words, the priority encoders will occupy a large area and power consumption will also be on the increase if the priority encoder is provided for every block of CAM. As the number of blocks increases because of the division of the array, the area thus occupied thereby and the power consumption proportionally increase further.
As a result, there has been proposed a content addressable memory in which one main priority encoder is provided for the plurality of blocks and a block priority encoder to be separately provided is used for the block in which encoding is carried out by the main priority encoder.
FIG. 29 shows such a content addressable memory (CAM). As shown in FIG. 29, the content addressable memory 200 is divided into four CAM blocks 202 and each CAM block 202 is further divided into eight CAM subblocks 204. A priority encoder 210 is structurally hierarchical in that there are installed four main priority encoders 212, each being intended for the CAM block 202 having eight of the CAM subblocks 204, and one subblock priority encoder 214 is provided every four CAM blocks 202. As shown in FIG. 30, further, the CAM subblock 204 comprises a CAM subarray 206 having a predetermined number of CAM words with predetermined word length and its control unit including a hit signal register 208 for holding a hit signal resulting from the hitting of retrieval data against a CAM word.
At the time of match retrieval in the CAM block 202, the hit signals of all words in each subblock 204 are held by the hit signal register 208 and a subblock hit signal indicating the presence of a match word in the subblock 204 is simultaneously generated by an OR circuit (not shown) of the control unit in each CAM subblock 204. On receiving the signal, the subblock priority encoder 214 (including latch circuit 216) subsequently generates a subblock selection signal indicating the highest priority CAM subblock 204 and the subblock priority encoder 214 also generates an encoded subblock address. On receiving the block selection signal, a switch circuit (not shown) of the subblock thus selected is then activated to transfer the data (hit signal) held in the hit signal register 208 to the main priority encoder 212 as an output signal. Thereafter, the main priority encoder 212 generates a hit memory word address resulting from the hit signal thus transferred and encoded in the order of predetermined priorities in the CAM subblock 204. The priority encoder 210 combines the hit memory word address and the aforementioned subblock address and outputs the encoding logical address of the hit memory word of the CAM 200.
In the conventional CAM 200 shown in FIGS. 29 and 30, the priority encoder (encoder) 210 comprises the main priority encoder (priority encoder) 212 for controlling the plurality of CAM subblocks 204 and the subblock priority encoder 214 for assigning priority to the CAM subblocks 204 for performing the encoding operation. The order of priorities is first determined among the plurality of the subblocks 204 and before being encoded, the output signal of the first priority subblock 204 is applied to the main priority encoder 212. The encoder can thus be made relatively small in configuration, whereas the circuit area relative to the whole circuit scale of the CAM 200 is reduced whereby large scale integration is made feasible.
Notwithstanding, subblock-to-subblock switch time becomes necessary until the encoding of the output signal (hit signal data (hereinafter called "flag data")) from the second priority CAM subblock 204 is started after the output signal (flag data) from the first priority subblock 204 is encoded by the main priority encoder 212 and output. In other words, it takes time to transfer the flag data from the hit signal register 208 of the second priority subblock 204 after an encoded address is output from the main priority encoder 212 and there still exists a problem arising from low encoding efficiency.
More specifically, there has been devised no encoder having the means of generating a signal for previously notifying or predicting the timing of terminating the operation of encoding flag data in the subblock (e.g., a termination notifying signal) and a signal for giving actual subblock-to-subblock flag data switch timing or the means of holding flag data in the second priority subblock at least until such a termination notifying signal is output in order to arrest the subblock-to-subblock switch time and to raise encoding efficiency in consideration of the switch time. Although a demand for a timing control circuit for detecting subblock-to-subblock switch timing is increasing, what is capable of outputting a switch timing notifying signal for previously notifying or predicting the termination of encoding the hit signal in the subblock (e.g., a termination notifying signal) stably with certainty has been nonexistent.
In this sense, a current difference detection circuit (sense amplifier) is used to compare a reference current for controlling the timing with the detected current so as to output the differential current. Although a differential current circuit of the static type has been mainly employed for the purpose, it still poses some problems one of which is that power consumption tends to increase because a steady state current flows therethrough and another one of which is that a relatively large area is needed for implementing a reference constant current circuit configuration.